Job description
Job Requirements
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
- Experience in all aspects of implementation like area efficiency and low power, timing closure, ECO implementation, equivalence checks, – UPF generations, and CLP
- Acknowledge about all libraries set:.lib/ .db/ ndm/ lef/ tlef/…
- Responsible for library control and understanding of standard cells/memory usage
- Responsible for the synthesis (blocks/chip top level) and SDC development
- Provide support and review constraints, reports, etc to ensure quality
- Collaborate with PD engineers for the netlist quality, SDC debug, Clock uncertainty definition for PnR, and sign-off
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
- New graduate student
- Major in Electrical – Electronics, Electronics and Telecommunication, Computer engineering Technology…
- Has thesis, essay, investigation related to VLSI, VHDL, System Verilog, Synthesis, Design For Test, Physical Design
- Used to have the internship course at Semiconductor Design Companies is a plus
- Good at English and presentation
