Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

• Key Responsibilities Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementation
• Do Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
• Do Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
• Develop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
• Implement, enhance and maintain Synthesis, STA scripts and various automation flows
• Work closely with logic design and PnR engineers on logic, timing, power and physical issues
  
  

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Work Experience

• Familiarity of ASIC design flow (FrontEnd, DFT, PnR)
• Hands-on experiences in front-end implementation tasks such as synthesis, constraint developing, timing, area/power analysis, linting, and logic equivalence checks
• Hands on experiences in EDA implementation tools for logic synthesis (DC/FC, Genus), RTL/Netlist Check (SpyGlass Lint), LEC (Formality, Conformal), Multi Voltage Verification (VC LP, Conformal LP), STA (PrimeTime, Tempus)
• Experience in multi-clock and multi-power domain designs
• Scripting and programming experience using Perl/Python, TCL, etc.
• Knowledge of RTL coding using Verilog/System Verilog or Physical Design is a plus
• High quality execution of high complexity work.
• Support customer presentations exemplifying our capability.
• Help answer team members’ technical questions.
• Quest Global standard work - creation and maintenance and support.
• Participate in technical reviews (possibly sign off on/conduct technical reviews). Peer Reviews.
• Mentor junior team member to develop capability.